Errata for Computer Systems: Architecture, Organization, and Programming by Arthur B. Maccabe, Richard D. Irwin, Inc., 1993 1st Printing (January 1993) This file can be obtained via anonymous ftp on ftp.cs.unm.edu in ~ftp/pub/maccabe/errata Last updated 10/15/93 Many of these corrections have been noted by Anthony Barnard at UAB. I am very grateful for his efforts in identifying the problems and their corrections. Thanks. ----------------------------------------------------------------------------- Preface. I neglected to acknowledge the efforts of Dave Hanscom at the Universtity of Utah who played a major role in my efforts to revise the first draft. Dave spent lots of time offering quick feedback on my plans to reorganize various parts of the book. In addition, Dave spent a day working with me to decide how to re-organize the first draft into the organization that appears in the final manuscript. With the amount of work that he put in to this project, it's hard to imagine that I was able to neglect his participation -- sorry Dave. I also neglected to acknowledge the participation of Stephen Wheat from Sandia National Laboratories and Bernard Moret form the CS department at UNM. Stephen and Bernard read and commented on my early drafts for Chapter 13. They gave me lots of useful suggestions that really improved the presentation in this chapter. Thanks (and sorry for the missing acknowledgement). p xiii, Steve Schach's name is misspelled ----------------------------------------------------------------------------- Chapter 1. p. 13, first line of section 1.2 should read: In Chapter 7, we will... (i.e., omit reference to Chapter 8) p. 18, in the second column of the table in the upper right corner, rows 2-5 all use the name DC1. These names should be DC1, DC2, DC3, and DC4. ----------------------------------------------------------------------------- Chapter 2. p. 39, the gate counts noted in Examples 2.3 and 2.4 include the delay for the not gate. In the footnote on the previous page I promised I wouldn't count not gates -- sorry. p. 39, the Boolean expression in Example 2.4 should have a negation bar over the right side of the equation. p. 44, the equation on the left side of Example 2.9 uses ci in the last term, it should be c_i (i should be a subscript). p. 52, the first equation at the bottom of Example 2.14 uses ci in the last term, it should be c_i (i should be a subscript). pp 54 and 55, in Examples 2.17 and 2.18, the labels Step 1 and Step 2 should be exchanged. p. 58, the D signal is inverted (it should transition from 0 to 1). p. 64, the last line of exercise 2 is ambiguous. Change it to read: For each of the following functions, show how the function can be implemented using a single gate with negation bubbles (you may use different gates for different functions): p. 65, Exercise 8, in the last line of part a, fuller adder should be replaced by full adder and a closing paren, ")", should be added. p. 66, Exercise 9, the last output should be labeled y sub 2 NOT y sub 3. p. 67, Exercise 20, the number of gates needed for a generalized and or or gate is HALF the number of inputs for the gate. p. 97, line 14 (the line with Transaction Master in the margin) replace transitive with transient. ----------------------------------------------------------------------------- Chapter 3. p. 91, Figure 3.13: INC --> PC & load PC should be moved from step 0 to step 2. (This avoids a possible race condition in setting MAR.) ----------------------------------------------------------------------------- Chapter 4. p. 119, Example 4.2: the last line should read ADD 100, 100, 200 ; a = a + t1 (i.e., make the code consistent with the comment) p. 127, Table 4.5: the semantics associated with SUB should be changed to read [Subtract] the value ... [from] the value ... p. 130 and 131, teh LOAD instructions use register R0 -- they should use register R2. p. 141, Example 4.19 uses the compare and branch operations -- the assembly code should be changed to: CMP R2, R3 BRGE false_lab CMP R3, R4 BRGT false_lab p. 144, Example 4.23: The comment (MOVED--branch delay slot) on the instruction ADD R1, R2, #1 should be deleted p. 150, Figure 4.5: The floating point format (third from the top) does not have an "i" field. The "opf" field should extend into bit 13. p. 157, Exercises 12--15: Assume that there is a branch delay slot. ----------------------------------------------------------------------------- Chapter 5. p. 168, Example 5.4: Add the folowing sentence to the example statement: In this case, you should assume that the location counter, $n$, is of the form $4x + 2$ for some integer $x$. For example, the location counter could be 2, 6, or 10, but not 3, 4, or 5. [See exercises 4.5 and 4.6 for further clarification.] p. 176, Figure 5.8: [24] should be changed to [23] p. 177, Example 5.10: the comments refer to R2 -- they should refer to R3. p. 183, Example 5.15: the last line should read STORE @R3, R2. p. 198, Section 5.7, fifth sentence: When [we] introduced... ----------------------------------------------------------------------------- Chapter 6. p. 219, Example 6.8 the last line should read BRANCH @R31 (not @R1) p. 220, the last line should read: any), along with the names and ... ^^^ (not any) ----------------------------------------------------------------------------- Chapter 7. p. 250, Figure 7.4 the outputs should be labeled z[n-1]...z[0] (not c). ----------------------------------------------------------------------------- Chapter 8. p. 291, Table 8.2: the entries in rows 1, 2, and 3 under the f column are incorrect. The second number in row 1 should be 0 ... 01; the number in row 2 should be 0 ... 00; the numbers in row 3 should be replaced by the word "anything". p. 293, Figure 8.6: the figure indicates that 25 bits are stored in the significand of the result -- only 23 bits are actually stored. p. 295, Figure 8.9: the significand is only 52 bits (not 57 as indicated). p. 296, Example 8.14: 1.5 in the solution should be changed to 10.5 ----------------------------------------------------------------------------- Chapter 9. p. 311, Table 9.3, in the first line, offset should be multiplied by 2. p. 312, Figure 9.1: there should be an arrow from the ALU to Bus 3 p. 339, Figure 9.14: there should be an arrow from Bus 3 to the micro branch register (uBR) ----------------------------------------------------------------------------- Chapter 10. p. 365, Figure 10.6: the declaration for the member name uses the wrong version of * (thanks TeX) p. 392, Figure 10.28 the $<$ in the first for loop should be replaced by < ----------------------------------------------------------------------------- Chapter 11. p. 412, Example 11.1: the third line of the example statement refers to the symbol "os_routines", it should refer to the symbol "routine_ptrs" p. 413, Example 11.3: the first line of the code should reference the symbol "os_routines" (instead of "os_routine"). p. 419, Figure 11.8: the two instances of "32" should be replaced by "31". p. 419, Example 11.8: 128 + 14 is still 142 -- replace 132 with 142. p. 419, Examples 11.8 and 11.9: the address 2,012 is incorrect it should be 2,272. ----------------------------------------------------------------------------- Chapter 12. p. 444, Example 12.1: in the third line of the problem statement change "(e.g.," to "(i.e.," also in the fourth line change "receive register full bit" to "transmit register empty bit" p. 444, Example 12.2: the last line should read: LOAD.b R3, UART_RCV p. 471, omit review question 20 (the text no longer discusses cycle stealing) p. 472, Exercise 2: first line: temporary differences [in] rates.... fifth line: at at faster rate than the UART [processes them], ... ----------------------------------------------------------------------------- Chapter 13. p. 493, in the illustration in Example 13.11, the rightmost p_0 should be labeled p_4. p. 497, third line from the bottom: NORMA machines have lead to .... should read NORMA machines have led to .... ----------------------------------------------------------------------------- Appendix B. p. 527, Figure B.3: the label "Status shift register" should be changed to "Receive shift register". ----------------------------------------------------------------------------- Appendix D. p. 546, the entry for "BIOS" should follow "BCD" the entry for "Big Endian" should precede "bias" p. 552, the entry for "locality" should follow "load delay slot" p. 557, the entry for "volatile" should follow "virtual processor"