A page table entry on a system has 4 bytes; the logical address includes two 10-bit
page addresses (it is a 2-level paging system) and a 12-bit displacement; the
physical address is 36 bits long. Design a typical page table entry for this system,
justifying every field.
Suppose the TLB hit ratio is 99%; of the logical addresses that cannot be
translated through the TLB, 5% provoke a page fault, while the other 95%
resolve the address through a page table entry. Further suppose that a TLB
look-up takes 1 unit, a page table look-up 5 units, and a disk access 10,000
units. The machine is a RISC machine, where each instruction references CPU
registers and at most one memory location. How many units per instruction
are devoted to address translation?
Does an inverted page table have to have one entry per page frame, or is it enough
to have one entry per page in main memory? (Are the two different?)
Can you think of a use for seeting up the inverted page table as an array of entries,
one per page frame, arrayed in the same order as in main memory?
We have said that procedures such as malloc or new are compiled (or
linked) into the user's code so as to avoid unnecessary system calls, but that they
can make a system call when they require another page of memory. That was under the
assumption that user requests are quite small and can be handled within the pages
managed by the local version of malloc. What if a user program requests one
very large block of space, a block that would span many pages?
Are there possibilities of deadlock with memory allocation in a paged virtual memory
system? of livelock? of starvation? State why not or give examples.