The Intel Paragon as well as the Pentium Pro based Teraflop computer to be installed at Sandia National Laboratories have the ability to dedicate a general purpose CPU to the task of sending and receiving messages. The CPUs share the memory bus with the DMA units and the network interface. A snooping cache coherency protocol ensures the integrity of data in the caches and main memory. In the message coprocessor mode, one CPU remains at the user level executing application code, while the second CPU remains in kernel mode polling the network interface. The two CPUs use a mailbox in shared memory to exchange information. For this to be effective, the second CPU cannot execute code in user mode. For our purposes, we let the second CPU interrupt the first one when it is time to run a handler. Figure 2.6 shows the execution flow.