In the Stanford FLASH multiprocessor architecture [40, , ] each node contains a custom node controller called MAGIC. MAGIC is located between the network and the CPU and memory. It consists of several queues and a protocol processor. The protocol processor has instruction and data caches, independent of the main processor on the board.
The protocol processor uses physical addresses to access main memory. Translation of virtual addresses and the necessary verifications are performed when addresses are transferred from the main processor to the protocol processor inside MAGIC. This gives the protocol processor the ability to transfer data to and from main memory very efficiently without affecting the operation of the main processor. That is, no interrupts or context switches occur on the main processor when new messages arrive. The design is very flexible and allows the implementation of a wide variety of protocols inside MAGIC.
MAGIC handlers directly control the message passing behavior of a node. Erroneous handlers executing on the protocol processors can corrupt data and crash the whole machine. Therefore, handlers have to be created and validated with the same scrutiny as the hardware in the system, making it impossible to run user-created handlers on the protocol processor. It might be possible to run the R-code interpreter on the protocol processor. This would allow users to submit code that runs (interpreted) on the protocol processor.