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good afternoon good afternoon so today we will look at bypassing and EHR so EHR
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is a new thing which you haven't seen so far in blue speck though you may have been implicitly using it because we have
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given you modules which could all be put together using EHRs but today you
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demystified and you can write your own you can use the hrs and produce more stuff right so by it bypassing it's a
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big deal which has been emphasized to you and lectures by semina and and and
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daniel at a very high level it's really an idea so that we can reduce the number
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of stalls something that takes multiple cycles can be done in one cycle if we
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can provide some way of reducing connecting the producer of a value with
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the consumer of the value so essentially bypass as the word implies is providing
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a path an extra path so for example normally you will write back into the
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register file and decode stage tries to read it so that's the normal path and a
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bypass essentially means that you're going to provide an extra path which bypasses the register files so as the
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value is being produced you can use it in the decode and if you can do that then it's going to save this cycle of
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storing it and register file in and using it later right now there are a
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couple of things which are just well known and yet it's hard to measure
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unless you have the right tools unless you do synthesis of your design and one of them is the benefits of bypassing at
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some level are very obvious to you you'll be able to see oh yeah I should eliminate a cycle here stall there etc
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but what is much harder to estimate is what impact it has on the clock cycle
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because bypass by its very definition introducing new combinational paths in
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your circuit right in your design and anytime introduce new combinational parts there
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is always a chance that that path suddenly becomes a critical path and therefore your clock period may get
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larger have to be larger in order to accommodate this by passing logic and
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this thing is something where you know intuition really is very hard to
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quantify it without proper tools so we'll show you some very simple examples of this
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the next question is that bypassing is a good idea but there is no such thing as
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a free lunch so there is some costs associated with it in terms of area in terms of clock periods perhaps and then
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you know should I do it or should I not do it so that depends very much on how
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frequently you expect that by path to be used if it's used often absolutely but
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if it's used rarely then its overall impact of the performance may be minimal
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so this is something else where we can do lots of measurements on the kind of programs running or the hardware you're
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designing how much impact will bypass have and this goes beyond hardware it becomes a issue about what kind of
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software is being run on top of your processor now when it comes to bypassing
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in blue speck you're not going to find yourself connecting this point to that point combinational II doesn't work like
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that right so there's a different higher level view of bypassing right so you
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think of it in terms of reducing the number of cycles it takes to execute two conflicting rules or methods okay so let
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me illustrate or let me ask you questions so suppose I want to build a FIFO right where I want to be able to
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end queue even though 5/4 is full because concurrently somebody is going
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to be D queueing it now obviously for correctness what you want is no nobody
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is D queueing it then it behaves like a full 5/4 you can't do an at that point on the other hand if you
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could detect that's all somebody is actually going to end cue sorry DQ at this time then you can also end Q so it
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looks like as if you include in a full FIFO so this is a slightly different way
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of thinking about you know the concurrent methods we have had so far where we just said oh this NQ + DQ can't
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be done together because there's a conflict of some sort right there I think the same register or something
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like that but there is a reason why we want to go beyond that here is another
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example which you have seen earlier so there are two rules here RA and RB and
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you can see quickly that they conflict with each other why because both of them you know first
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one writes in X and the next one writes in Y and the first one reads Y and the
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next one reads X so there's sort of a cyclic dependency in these rules conflict because you have to schedule
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them one by one but you can ask the question what will happen if I really want to execute them
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in the same cycle what is preventing me from executing them in the same cycle so what you somehow want is to communicate
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this value of x from rule RA to RB right in the same cycle if possible as opposed
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to waiting for it to go into the register and then coming back you should have a bypass for register X and if you
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can do that somehow then it may be possible to execute these rules together and if you execute them together then
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it'll behave as if rule RA happened before rule RB so I'm giving you very
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high-level issues here you know where I have a very clear goal what I want to do
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and now the question is we will discover very soon that the only solution to these things is introduction of bypasses
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so we will also introduce bypasses that is in a very different way at significantly higher level then it's
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done in traditional digital design right and the these kinds of designs that I'm
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mentioning on this slide are not possible the subset of blues fake you have seen so far okay so why is that limitations
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of registers if you want because that's the basic abstraction on which the whole
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thing is built up in blue spec okay so when you use registers for communication
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right in the same atomic action certain
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kinds of communications are just not possible so for example if you are writing into that registers you can't
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read it in the same cycle you read it in the next cycle so what that does is that two methods can't communicate as you
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just saw between RA and RB because X is being written here and to preserve the
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semantics I want this X to be visible here well then I have to wait until the next cycle okay so if if you could you
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know if there is a desire that two methods communicate with each other in the same clock cycle in the same atomic
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action then something is needed because registers are not going to let you do it similar issue arises between two rules
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and two methods and between a rule and a method so in all these things if a
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register is being set it can be read by the other entity only the next cycle and
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this is what we want to get over we want to you know see how to solve this
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problem and actually there are quite a few solutions and I'm not going to give you the history of them and you know it
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depends I sigh in the eye of the beholder but some of them are pretty ugly they will turn blue spike into from
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a high-level language into a very low-level language so this is the solution that I like best which is
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called EHRs EHR stand for ephemeral
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history register a mouthful of a name and I won't go into why we named it like
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that but EHRs is it a primitive element to design modules with concurrent
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methods so in other words what I'm gonna do is until now you had a blue speck
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with registers now you're going to have a blue speck with registers and EHRs do
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an EHR can to be used as a register ordinary register so HR in some sense subsumes
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the register but let's not mix them up I mean when we use EHRs I want to use it
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explicitly so that you know what you're doing with this okay
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so this idea was introduced by John Rosen banded his thesis and there are many many interesting aspects of that
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work but just imagine I'm designing a module and what is my register with
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enable that's what I have shown you on this slide right you have a flip-flop and you know you keep feeding it back so
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if there is a new right coming in it's enabled then the new value gets captured otherwise it doesn't change its value so
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that's what reads and writes behave like an ordinary register so this is the normal behavior and if you do them in
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parallel it behaves as if we'd happened and only after that right happened
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because the effect of right can only be seen in the next cycle so far so good
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all right so now I'm going to embellish this a bit extend this a bit how about
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this suppose I also provide another port on my register which takes this output
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and puts it out so what is r1 now
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how does r1 behave it's actually going
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to read the value if the new value is going to be written in other words if if
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you have you know Arvin returns the current state if w0 is not enabled so if
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nothing is enabled it's just like r0 on the other hand if w0 is enabled
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sometimes is trying to write into this register then r1 will see that value which is being bypassed it's a bypass
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spot you know you can see it even though the register anybody who's reading r0
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will only see it in the next cycle so here is a register element where I'm
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giving you both I'm giving you the normal read and I'm giving you the bypass read from it
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so that's half the idea of EHR the second idea is that we are also going to
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give you another right which is prioritized right so if you have w0 and
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w1 and both are enabled then I want the system to behave as if w1 is the one I
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wanted so you mean the same clock cycle if you want to do w0 and w1 I want w1 to
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prevail and this is this can be done simply by the circuit so I take
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something that is coming from you know w1 and then if w2 was sorry W 0 and if
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w1 was also enabled you know we will select that using this enable and that is the value that will be stored in your
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register and if you do it like that then you know it's very clear that W 0 comes
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before W 1 though there is no guarantee that either will be enabled so you have
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to understand the behavior of the circuit you know when neither w0 and w1 is enabled somebody tell me what do
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reeds look like in that case it'll be the old value whatever was
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stored in you know register beforehand that's what you will see suppose w1 is
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enabled then what will happen I keep
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though I keep jumping suppose w0 is enabled what will you see
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so r0 will still see the whole value or one will see the new value that is
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coming in and what will I see in the next cycle the value that you just wrote
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right w0 is what will be visible in the next cycle now tell me what will happen
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if w0 is not enabled but W 1 is enabled
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W 0 is not enabled but W 1 is enabled yes yes and what will R 1 C very good so
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both of them will see old value but the value that will be stored in the register is the new one right is the W 1
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value that you're writing and now it's a easy extension suppose both of them are
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enable tell me what will happen yep
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so in the next cycle I'll see w1 fantastic so everybody got it so
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functioning of this is straightforward but like in most things in Duisburg we
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don't want to think in terms of low-level circuits we want to think in terms of some high-level thing and that
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would be an EHR declaration so anytime you do any HR you're gonna get this for portrait device to read ports and to
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write ports with its own behavior so we
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like to capture these things in terms of conflict matrix just a reminder the conflict matrix for a register was
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simply that to write reads of course don't conflict with each other and two
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writes into the same registers of course conflict with each other but if you do them simultaneously it looks like
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register read happened before the right right so that's what is captured in this
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and now based on this I want to derive the conflict matrix for EHR so I filled
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out the part which is just like the register right I mean if you're just focusing on W zeros and are zeros you
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know it's just like the old stuff all right so now tell me what should go into
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eh r dot R 1 right if you are writing something at that point so it will be
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it'll look like as if the right happened and then the read r1 happened right
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because by design that's the bypass you know you're seeing it you know come after that and the reads of course you
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know remain conflict-free and these things always have a duality so if you think so these things then the
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you can fill out the diagonally opposite entries in a similar way all right now
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what about does this make sense by definition w0 comes before w1 you
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have seen the circuit right so if you are trying to do w0 and w1 in
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the same cycle it'll behave as if w0 didn't happen you know you will just
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read the w1 value as far as storing the value in the register is concerned so
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that's why you have that and again by symmetry you will have this over here now what about our 0 and w1 so you are
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reading our 0 and somebody is writing in
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w1 it will be that you know you will see
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it in the next cycle you are not seeing it right now right because you only see what was
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being written in I mean you know this
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this is I was talking about how do I I should be pointing I'm looking at this
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entry right so if you are reading something here and writing in w1 you
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won't see it right now right you'll see it only in the next cycle so that's why it's less than that all right this is
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obvious that our ones are conflict free and two people writing into W ones will
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definitely be a conflict it's like the same double use of a port never allowed
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and you can argue out what this entry should be so you know it may take some
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thing but given that diagram and your understanding you should be able to fill this out so when you design this circuit
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this is the kind of conflict matrix that would be generated but I do not
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recommend you design this circuit because this cannot be designed by you you know it requires some very low-level
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hacking inside do spec so from our point of view we're just going to use EHR as a
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primitive you're going to use it just just as we have used resistors now we're going to use EHRs also as a primitive
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and now what I'm going to do is actually do some practice let's design a few
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things using EHRs so what we're going to do is design a pipeline FIFO you know
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which allows you to in tune to a full five for as long as there is a
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simultaneous DQ going on and we will design a pipeline FIFO which will allow
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you to DQ from an empty five four provided somebody is in queuing at the
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same time you know the value will slip through it and you will see it at the output and we will design a
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conflict-free FIFO which we had done earlier but our conflict-free five four had a dead cycles right you could do
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reads and writes but then you had to wait internally for canonicalization so from outside you couldn't tell but from
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inside you'll be able to see that we can design a more efficient FIFO of this
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sort where nqd could do not interact with each other they can be done concurrently and there is no debt cycle
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you can keep doing n qdq every cycle in this FIFO okay
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so what I want to show you is that whatever work you have done so far is already very useful we can use that and
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transform those five five fours in a very systematic way right to generate
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the FIFO of our desired so let's look at this so this is the one element five
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four from lecture 17 or even earlier I think and here's the conflict matrix you
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know you know n qdq can't fire together because they you know mutually exclusive
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parts of this so this is the one element five four we had earlier very very
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straightforward to write but doesn't have exactly the properties we want so the question I'm asking is can I convert
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it into a five four where n Q will happen before D Q or can I convert it
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into something where n Q will DQ will happen before n Q in other words can I
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transform this into a either a pipeline five four or in a bypass five four
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okay so let's see how does this transformation work I have copied the code again here and now this is the
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conflict matrix I want in this so what
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is it that I want I mean if I want to be able to in queue in a full FIFO then I
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have to know if DQ is happening right if DQ is happening then I can do the NQ
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also so what that is saying somehow is if V is being written right by DQ if I
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can communicate that information to the NQ well then maybe I can do something
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about it right because what dairy registers do not allow this communication you know two methods
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cannot talk each other except through the next cycle I want to do it in the same cycle any ideas how we'll proceed
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with this what is this reminiscent of
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somebody is writing into V and another method bonds to read it in the same
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cycle what does that remind you of
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we need a bypass right of some sort okay so let's replace this V by an EHR so EHR
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you know I'm just dealing with two reports to write ports but you're gonna have VH ours with n ports if you want so
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that's why that 2 is written here ok otherwise it's just like a register you
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know it's type is boolean and it's initialized to false
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okay so when you have this what I'm gonna do is I write M v-0 and DQ and I
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read in the same cycle so I am reading the bypass path from there how many
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people understand this okay so what was
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happening in DQ I was writing in V right so now I'm going to writing in me same
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as writing V dot you know zero in that right I mean that's the first port I was
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writing into it but the change I want is in my NQ procedure in my NQ method I
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want to be able to see this right away as opposed to the next cycle so I want
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the bypassed version of it so which is the bypassed value coming out of V V one
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right so we you can write in V 0 V 1 you
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can read V 0 and V 1 so when you write in V 0 and you read me one you are
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actually reading that value at the same time we are not done yet this is just to
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establish some you know at least we can communicate right so first of all the
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moment you have made it in EHR this has become an illegal program because their RVs here which are not be a charge so
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you make up your mind whether it agrees a register or with an EHR if V is an EHR then all the V's have to be changed so
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that's the next question what should be the V in the DQ part when you're reading
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it it should be zero right because you're
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seeing the current state you know it is their space in it you know - is there
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some sorry is there some value in it okay so this has to be easier
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please ask questions whether I'm seeing too many blank faces here what have I
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done by doing this yes because I could
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give you a long-winded answer but the first one is reading the current element
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you could have defined it different first you could have defined the first which is just going to read what who
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came in but that's not what we are trying to do our only goal was that we
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want to be able to end you in a full FIFO so you can experiment with that I
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mean if you wrote it as v1 you'll get a different fire yet and not all of them will make sense I mean do say how will I
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use that one you know this one is has a very specific purpose in mind who's but
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you can try to design something with all kinds of funny entries this so what was
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I going to say about this yes so remember our goal in this thing is that
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NQ sorry DQ happens first and then NQ happens whenever you have such a clear
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understanding that means anything that was going to happen first put zeros in it everywhere because you want it to
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happen right you don't you're not depending upon anything else so therefore in DQ you have v-0 and
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you're writing in b0 and you are saying NQ will happen afterwards right so what
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does NQ do it was reading V so we already agreed that it should do maybe
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one and not v-0 because we want this communication and what should happen to the Viets writing
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it should be v1 right who's gonna argue with me that that's the right answer
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what happens if you do NQ & DQ simultaneously this is the one element FIFO it'll save me full right and we've
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had something in it now it's gonna get something in it again so you won't be one to be true so previously what was a
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conflict that we was getting false and V was getting true as I make up your mind
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we have resolved that issue we say you know it can get a zero it can get a true
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or a false but in this case v1 has priority over it right it has precedence if if you are writing
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something in v1 and that will prevail it doesn't say that somebody is writing in
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v-0 but if somebody is writing in v1 that's the value you're going to get the next time so that's what happened here
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that and again it's very mechanical if you want NQ to happen before after DQ
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then in DQ everything is zeros in thank you everything is once
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more questions okay so basically what we
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have done is you saying NQ sees dqv has the right value in all
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cases so there are quite a few cases which you have to analyze that NQ is being done not being done DQ is being
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done not being done nothing is being done right so in all those cases you must end up with the right values for V
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and D otherwise your implementation is not correct I'm a happy camper you know
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so I got I use my ordinary FIFO and after a while you'll get so good at it
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I give you an implementation say what do you want you want this before that okay these are the things I have to change
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and you'll just go and you know introduce EHRs and use the proper ports into your EHRs to achieve that goal
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let's do a few more exercises okay so let's now make a bypass FIFO so by PI's
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five four is opposite we want in bypass FIFO two in queue to happen before DQ
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right that's like saying that I want this value to be communicated here because if somebody is in queuing then I
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want to be able to read that value now I want to be able to sense that oh something like this was happening
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and in order to do that I'll have to change again to this V has to be changed to VH ours and view you'll change all
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these values accordingly because if I write V 0 in NQ then DQ when I read V 1
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I'm seeing the latest value I know that somebody wrote it but this is not a
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complete picture because there is a D in this picture - and what DD want to see
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when you return D right this is the do you want to see so that
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means if I write in d0 down here I must be reading d1 if I want to read the same
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value in the first operation that I perform on it and if you do that that means D also has to be changed into an
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EHR are you getting the basic idea
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behind the hrs that instead of introducing bypasses everywhere
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we have encapsulated them in this new register element called EHR and we will
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use EHRs to introduce bypasses everywhere yes
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andcue have oh because this is a bypass 5-4 as opposed to a pipeline FIFO so in
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bypass five for the idea is suppose the 5/4 is empty so that means you can't DQ
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from it right on the other hand if somebody is NQ I could be clever and immediately pass it on right so that's
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what the idea is that NQ happens and then DQ will sense that same thing is true for first okay so again the same
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stuff no double right errors even though two people are writing because they're writing in different ports now and when
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they write in different ports we have defined the priority that port 1 has higher priority than port 0 very good ok
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so this was our 2 element solution 2 element FIFO where we were successful in
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making NQ & DQ conflict-free but there
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was this internal rule called canonicalize you know so you happily did your NQ and DQ and then they were sort
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of cosmic silence for a cycle right but internally something happened right it
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got into the right shape and then you could do more in queues and DQ's and this was explained in this conflict
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diagram when I included the conflicts with canonicalization canonicalization
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was mutually exclusive with all the other methods in the system and suppose
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I don't want that suppose I really want canonicalization to happen as soon as I
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am done doing NQ and DQ or either NQ or DQ I want canonicalization to happen all
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the time and not take an extra cycle can we transform this program and by the by
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now all of you know the trick what's the refrain
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replace all registers by EHRs right
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what do you want to happen first NQ & DQ
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should happen before canonicalization then NQ & DQ are happening in parallel so they are conflict-free with each
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other so there are all zeros right so this is what I I do here by reading
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zeros what you're implying is anything you do right is based on the old state
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whatever was in the system because I'm not reading any by past value same thing
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is true for the NQ pot in this write DQ
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part sorry everything is zeros we could do this much before we knew that I mean just
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using registers NQ & DQ were going in parallel our only problem was canonical
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couldn't execute execute because it conflicted so now what are we going to
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do to count our canonicalization rule is
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just waiting for all these other methods to execute right and if anybody executes
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they'll be writing in 0 so it's going to go and read once it does bypassing so this is the solution here you know I
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have replaced everything in the canonical methods with zeros by ones so
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by definition canonicalization is seeing the updated values right all the values
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they haven't been updated in the register yet but we have provided extra pass extra paths we have provided
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bypasses so that they can all view the values that are coming in to NQ & DQ etc
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so now this FIFO is wonderful because it's conflict free and you can keep
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doing NQ & DQ every cycle in it there is no dead cycle in the middle
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okay very good
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now we can keep doing this to all kinds of modules so we have a register file
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right and what is the normal view of a register file that reads happen before
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right in other words if I do simultaneous reads and writes I read the old values
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from the register file and whatever I write will be visible in the next cycle straightforward code to write and now
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suppose can I make it into a bypass register file so that on my reads if you
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were writing in the same register I want to see that value so that's the idea of
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a bypassed register file so it should behave as if the right happened and then reads happened it turns out to be a
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pretty useful thing that we use right so let's try to implement this then if we
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continue with this idea that we have so far what we could do is the following
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I can just declare the whole register files to be EHRs so each element of my
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register file is going to be an EHR right and does this code make sense
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I change the declaration so that instead of instantiating registers I'm in shat in sign feeding EHRs and then when I
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read sorry when I write I write in it's it's w0 I write in the port but when I
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read from the register file I'm reading
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or once from it so this will automatically capture anything that was
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coming in and we will be reading out not a difficult thing to do but to most
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people this seems like an overkill right because you're doing this one right and
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you have turned the whole register file into a you know EHRs you know which is a
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lot of logic is there a better way of doing it right which takes much less
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hardware alright so let me give you another design for this which will we
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keep our old-fashioned register files and we put some new logic outside it
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some funny logic outside it so that the whole blob will behave like a bypass register file okay so how does this work
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the idea is very simply the following instead of directly writing into the
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register file you write into a FIFO okay
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and whenever you have to read something instead of reading from the register
37:31
file first you try to find it in the FIFO if the value exists that means
37:37
somebody try to write it you want to read that one if you don't find it there then you go in need it from the register
37:44
file and at your leisure your leisure
37:49
better not be too long you can move these values from the 5/4 into the
37:56
register file whenever you find time just move it from here to there I move
38:01
it from register file to from 5/4 to register file is the high level plan K
38:07
at every one yes no okay let's try it again
38:15
so I have my ordinary register file which keeps all values right but every
38:23
time you do a write I create a small buffer here so I'm new values are being written here because I may not have had
38:29
time just to go and update the register file so whenever you do a read before reading the register file I just read
38:36
this buffer first say is there a value for register R in here yes then I read
38:41
that one if not then I go and read the register file so that's the whole idea that is trying to be captured in that
38:49
diagram that is shown up there where RF is the ordinary register file and this
38:54
whole blob will behave like a bypassed register file okay so help me write this
39:00
code so what will right do what does register write do sorry register file
39:07
right do in this case is just gonna
39:14
write into 5/4 right so you you have oh I need all these declarations then my
39:20
register file is ordinary and I have introduced a 5 for bypass FIFO in there
39:29
and so I'm calling this 5 for bypass because that's what I'm keeping all the
39:36
bypass values so I have now include a value into the bypass register file
39:42
that's all that's all register right does what does it just a redo who's gonna
39:52
tell me at high level yep
39:59
very good so we go to bypass rod you
40:06
know I'm being fancier you know my I'm assuming FIFO is very big it's really one element so it's a very simple test
40:11
so there is no search going on per se but if you had two elements then you would have to write more code but I'm
40:17
just writing it more abstractly right so you can search the FIFO and if you find this value then you will return it
40:26
otherwise you know this is what is being shown here that if it is not in the
40:35
bypass FIFO then I go and read it from the register file otherwise I just read
40:40
from the bypass fivefold in this and the
40:45
second read is exactly the same because it's a two ported register file there is no change in that so far so good so we
40:55
are reading from here we are writing into this but somehow we have to get
41:01
things into the register file - yes I'm
41:08
coming to that okay so that's the thing that is written at the bottom what you
41:16
have your five phones right of any ugh so this has nothing to with bypass or not bypass ordinary FIFO and now I'm
41:23
gonna provide you an extra function on it search right so for that your you
41:30
know you can search on anything inside the FIFO but generally we think of it as a key value pair being inside the FIFO
41:38
but you could have search on any bit pattern in the value so you define the
41:43
search function when you make a searchable FIFO and it will just go
41:48
element by element and returns the value it tells you whether it found it or not
41:53
the many many possible designs but in this case it's in total overkill because if you have a one element FIFO you can
42:01
write down all the logic yourself of the searchable FIFO but in the library you
42:08
know you'll find s FIFO so anything is you cs5 for that means a searchable FIFO
42:14
okay and then you have this move function a move rule so what is the move
42:20
rule doing yep so now I want you to take
42:35
it a step further tell me when does this we'll have to execute
42:44
must execute them suppose I don't execute it what will happen sorry
42:56
right so what'll happen it will try to build a you know your this bypass FIFO
43:03
has to be bigger and bigger right if you don't ever write it but five bypass five
43:09
for itself is fixed size one element or something so how will this register file
43:14
behave if you don't execute that rule
43:22
well we can't afford to lose all right right exactly so remember in blue spec
43:30
every method has a ready signal until
43:36
now the register file behaved as if the ready signal was always true now what
43:43
will be that ready signal for the right
43:48
it'll be the ready signal of the who's
43:55
going to help you here bypass FIFO right so if bypass FIFO has no space left in
44:01
it means a sorry so he can't execute this can't do this in cue that means the
44:07
outer thing will stop what I'm trying to show you here is blue speck at some very
44:14
high level remains a extremely time independent model right so whenever we
44:22
argue in terms of cycles whenever we argue in terms of concurrency it's always so performance which is extremely
44:28
important but performance is not any more important than correctness and whenever you argue correctness you can
44:35
see this is getting too much for me I'm going to argue one thing at a time right let's do this first let's do that first
44:41
and that level of argument is also always valid in blue spec you can think
44:46
of your designs regardless of how many things are happening concurrently one at a time time even after EHRs everything has a
44:55
proper meaning one rule at a time we do not sacrifice one rule at a time
45:00
semantics of blue spec just because we have introduced by passes in EHRs so
45:07
that's really the at a deeper level that is the invention here otherwise EHRs would have been just a hack but it's a
45:15
hack with very very good theory associated with it you know you you're eating your cake and eat you know what I
45:22
miss my metaphor when you get the point eat your cake okay so we will have a
45:37
register file design this way and now you know if we really want to be honest you should go and synthesize a register
45:44
file using EHRs and synthesize the register file using this stuff and see
45:49
you know what are their properties which takes more area which takes you know which has better delay and so on so
45:56
don't take my word for it if you want to and synthesize both these things and you see the difference okay now what I've
46:07
shown you so far is actually interesting that I can take these modules and I can
46:12
derive many derivative modules right which has the same functionality but
46:17
they have different concurrency properties to them which is extremely useful for me to design these systems
46:25
and this idea can be applied to many different things I just showed you two
46:30
examples five force and register file but you can do score boards this way you
46:36
can do memory systems just provide so many variants because of this you know
46:41
because in some places in memory system we absolutely cannot afford to lose a
46:47
cycle right because it'll be just have plastic consequences for performance in
46:52
many other places we don't care if extra cycle gets introduced and if you are wasting too much time with bypasses
46:59
there you're wasting time okay now the good thing about such users
47:05
of EHRs is outsider doesn't have to know anything you know so you're an
47:13
introductory class well you guys are very advanced but you know if you didn't understand EHRs and somebody says don't
47:20
worry about it here is a module use it here is a bypass five for use it here is a bypass register file you use it in the
47:27
rest of your design you don't have to worry about EHRs you can just use these modules as they are in a blackbox manner
47:34
so we deliver on that promise to you know that whenever you use these things we do not break the black box model of
47:43
use of various modules in the system but what can happen when you use such
47:50
modules is that it can affect the delay of combinational parts because you know
47:56
there is no free lunch whether I'm going through bypass five four I'm introducing explicit bypass there is a bypass at
48:04
work and anytime there is a bypass at work you can make the combinational
48:09
parts longer and that makes things worse right so let me just quickly illustrate
48:16
that how this shows up so you may recall this from an earlier lecture right so we
48:24
were designing two stage pipeline and we were trying to resolve you know the
48:30
control hazard you know so we were speculating and then we did a very good design where PC is being updated here
48:37
and a PC is being updated there and we had epics and everything and you know
48:43
two rules conflicted because they were both writing in PC so it turned out to be a bad design it produced right
48:49
results but it was not any faster than multi cycle version of it now if I had
48:57
taught you EHR s earlier all of you would have said oh use EHRs why because
49:04
we are using you know we are updating here and we are also updating here which
49:11
caused a conflict and therefore these rules became conflicting with each other now you have
49:17
this big weapon in your arsenal called EHR what will you do
49:34
[Music] did everybody get that turned PC into a EHR right so instead of using an
49:42
ordinary register use it as an EHR and it has two input ports right so I will
49:48
write here and I should be allowed to read this thing in the fetch pot and
49:55
let's do that so when I do all this what happened right so I have turned PC and I
50:02
you will realize you have to do this to a pack also so what you will find is wherever I was using PC whenever I was
50:09
writing in PC I'm writing in PC 0 here and I'm you know reading epoch 0 I'm
50:15
writing an epic 0 but in the fetch stage because I want to see what happened
50:21
later on right in my pipeline I want to know right away what what happened because this is the older stuff that is
50:27
happening so there I read EC 1 so you updated it in the execute stage and we
50:35
provided a bypass from this to the fetch stage so there you can read it you know what's in the what is the new value of
50:42
PC that somebody wants to write who has
50:54
the authority in this who knows the who should prevail in case of you see
51:00
remember the first one the fetch stage is speculating right so this is the
51:07
thing whatever it does should prevail because fetch stage comes after me I
51:12
mean you know it comes before but the older instruction has the authority to
51:18
update everything so that's why this happens first and then you will do it over there but these are exactly the
51:24
kind of questions you will have to face and I just wanted to show you what happens when you do this
51:31
first this last stage and last one is the one that is done using EHRs see what
51:36
happens to the number of cycles they drop dramatically
51:43
they dropped so much you know because the moment you see it when you go and
51:48
update it you know at the same time but because there is some extra bypassing
51:56
going on here right indeed the critical path became longer and that is affected
52:02
in this bottom row here that you know we were getting these kinds of timings you
52:07
know before 4 o'clock period and now suddenly went by more than 120
52:14
picoseconds no free lunch right and so
52:20
therefore you have to look at the multiplication of the two things generally I would say use EHRs if you
52:27
are using it at like this very very carefully very carefully because in big
52:33
design this gets harder to analyze you know what's happening so in modules yes you know because they're short bypasses
52:40
going on and we can analyze the effect when we use it we can plug in this module versus that module but when you
52:46
use the hrs at a higher level then there is many other things going on in the solution I think that's the there are
52:53
other things I could have told you but this is more than enough for yeah I would have told you how you can use the
53:00
ideas in the project but you you have that slide so you can see it good thank
53:05
you