To cover the basic SPARC trap mechanism and trap instructions.
After completing this lab, you will be able to:
Figure 16.1 presents the fields in the processor status register.
Figure 16.1: The processor status register
As noted in Lab 1, the SPARC uses separate address spaces for data and text (code). In fact, the SPARC provides (at least) four address spaces: the user instruction space, the supervisor instruction space, the user data space, and the supervisor data space. When the processor is in user state, instructions are fetched from the user instruction space while data values are loaded from and stored to user data memory. Similarly, when the processor is in supervisor mode, instructions are fetched from supervisor instruction space and data values are, by default, loaded from and stored to supervisor data memory.
When the processor is in supervisor state, you can use special load and store instructions to access data values in alternate memory spaces. For examples, you can load a value from the user data space, or store a value into the user instruction space. These instructions require an explicit address space indicator (ASI). Table 16.1 summarizes the ASI values used for these instructions.
Table 16.1: Address Spaces on the SPARC
The functionality provided by this trap is not absolutely necessary. Application programs could attain equivalent functionality using multiple invocations of trap 1 (putc). What is the advantage of providing this as an separate trap?